OPAL-RTカンファレンス Real-Time2023開催レポート

RT23で報告された、先端的なリアルタイムシミュレータ関連の各講演を紹介いたします。

RT23 |Vision-guided Autonomous Lunar Lander Simulation- a Hardware in Loop (HiL) Simulation

Author : Amitava Gupta

The study presented in this paper is an approach based on HiL Simulation to simulate the Powered Descent (PD) phase of a Lunar Lander using a representative physical model, a specified descent trajectory with velocity and attitude constraints and actual lunar imagery obtained from publicly available lunar image databases and other restricted sources . A 3-phase lunar landing is assumed consisting of a coasting Descend Orbit (DO), a Powered Descent (PD) and finally a Terminal Descent (TD) phase. It is further assumed that the lander is equipped with multiple sensors like the Inertial Measurement Unit (IMU), a surface tracking camera and Pulsed Laser Altimeter (PLA). The attitude and kinematic control of the lander is assumed to be guided by signals derived through sensor fusion .While the lander craft and its on-board controllers are simulated on an OpalRT OP4500 platform, the image processing hardware is interfaced through MATLAB. The final solution envisages a compact micro-controller based operation with an image processing FPGA and a processor core on the same board which is under development.. To eliminate the risk associated with manned lunar missions, autonomous lunar landing has emerged as the state of art in deep space exploration. Examples are the recent Chinese and Indian lunar expeditions. Autonomous Vision based hazard detection and avoidance system is one of the key research areas behind any autonomous landing mission for safe and soft landing on a planetary body and a comprehensive survey of these technologies is available in contemporary literature. The foremost amongst this is the NASA’s Autonomous Precision Landing and Hazard Avoidance Technology (ALHAT) . More recent developments include NASA’s Co-operative Blending of Autonomous Landing Technologies (COBALT) or the ESA’s Navigation for Planetary Approach and Landing (NPAL) use Vision Guided Control and Navigation (VGCN) which use real-time feature extraction for navigation of the space craft to designated co-ordinates (kinematic control) and also for correction of positional and attitude sensor data. A fantastic re-construction of the Change-3 lander’s actual descent trajectory is also available. The PD phase for the study presented in this paper starts at d 15 kms and during this phase the space-craft is subjected to deceleration in the horizontal plane as well as in the vertical direction by firing its thrusters. . The controller is a Hybrid Finite-State-Machine (FSM) based adaptive Proportional-Derivative (PD) controller and the velocity errors are corrected by adjustment of vertical thrust and attitude angles with suitable gain scheduling. The space craft relies on on-board IMUs and Terrain Relative Navigation (TRN) [10] using real-time feature extraction and matching across successive image so as to correct IMU errors. This phase , for the present study, is assumed to continue up to about 1.2km from the surface when the TD phase starts and the control set-points for navigation are generated at a faster rate i.e at 1 sec. interval for tighter position and velocity control. When the lander is within ± 1Km of its desired landing point in the horizontal plane and the velocities in the horizontal plane are less than ±10 cm/s, attitude stabilization is initiated so that the optical plane of the ground tracking camera is aligned with the central plane of the lander and the lander’s laser altimeters are switched on. The lander then descends to an altitude of approximately 140m and starts hovering using the on-board reaction wheel to create yaw around the z axis to detect minor hazards. If hazards are detected , the lander performs a re-targeting maneuver to perform a translation to a hazard free zone and touches down with a velocity of 1.8m/sec having engines switched off at 1m above the lunar surface. The entire simulation has been carried out on Opal RT with representative lunar data and imagery on an OP4500 platform.

RT23 | Experience with Hypersim on developing Digital Twins of modern power grids

This presentation aims to share our experience with using OPAL-RT and Hypersim as an enabling technology for building a Digital Twin in the context of the HP2C-DT project. This project aims to develop an innovative power network Digital Twin (DT) concept, able to represent with a high degree of fidelity modern power systems in a wide variety of applications, such as transmission, distribution, generation, railway and industrial networks. Different definitions of DT can be found, but a common definition is that data flows between an existing physical object and a digital object, and they are fully integrated in both directions. Therefore, what is unique about DTs is the bi-directionality feature. The project is developing a High-precision High-Performance Computing-enabled DT (HP2C-DT) able to capture, with a high degree of fidelity, modern power network dynamics, in order to maximize their resilience and real-time performance, autonomously acting over the system in a locally distributed (edge) framework. Several tools are being developed based on the DT, such as A. online stability and interaction detection tools (avoid potential instabilities), B. Real-time network performance tools (optimize in real-time the performance of the network), C. Protection tools (adaptive protection based on real-time measurements), D. Probabilistic scenario generation tools (analysis of multiple time-scale scenarios, for preventive decisions) and E. Autonomous real-time control tools (DT autonomous decisions over the power network in closed-loop). The presentation will show our experience with Hypersim on creating the Digital Twins of power grids.

RT23 | WELCOME TO RT23 and Keynote 1

RT23 Keynote 1: Pierre-Francois Allaire, Jean Belanger, Frederic Monfet, Etienne Leduc, Timo Roesch, Jean-Nicolas Paquin and Brad Armstrong

RT23 | The Transformative Impact of CHIL on the Development of Hydro-Québec's PHIL System

Author:Olivier Tremblay

Dive into the intricate world of Hydro-Québec's PHIL (Power Hardware-in-the-Loop) system development in a presentation led by Olivier Tremblay, D. Rimorov, K. Slimani, and R. Gagnon, research engineers at Hydro-Québec (IREQ), along with Benjamin Couillard, an engineer at Gentec Hydro-Québec and IREQ. The session offers a comprehensive overview, covering the context and motivation behind the PHIL project, power amplifier design, control system board development, and the critical role of the CHIL (Closed-Loop Hardware-in-the-Loop) environment. Explore the challenges encountered in developing a custom MW-Scale PHIL system, including the intricacies of power electronic converters design, microelectronic design, control algorithms for Active Front-End (AFE), and closed-loop control for EMT-type PHIL. The presentation concludes with insights into the pivotal role of simulation, particularly CHIL, in the development and validation of Hydro-Québec's PHIL system.

RT23 |Aircraft actuation system development with Power Electronics FPGA-based motor model

Author : Pawel Jastrzebski / Anna Kozioł

We present an application of Opal-RT Power Electronics (PE) technology for Hardware-in-the-loop testing of the airborne electronic controllers developed in our research and development department. In Woodward, we rely on PE models of inverter and BLDC motor to verify operation of our system. The application of FPGA-based PE solutions enables us to configure and virtualize physical components running tests in real-time with response time in microseconds regime. Full Opal-RT technology support for NI platform enables us effortless integration of the solution to our Test Stations built with NI PXI and NI Veristand engine. The PE models fits our needs both in the area of prototyping, development, and further system level and black box tests.

RT23 |HIL validation of isolated DC-DC converter in a MVDC network

Author : Titouan Abiad

SuperGrid Institute is an innovation and research company, expert, among others, in the development of HVDC and MVDC technologies. Since 2016, SuperGrid Institute has been working with Opal-RT to create and improve a Hardware In the Loop (HIL) platform that supports research and allows testing newly developed technologies. Currently, SuperGrid Institute is developing an innovative DC-DC converter which will be implemented in a demonstrator of a PV power plant based on MVDC collection network. This MVDC network (+/- 5 kV) is powered by solar panels arranged linearly over approx. 1 km and will reach 750 kW. It is composed of 3 DC stations spaced approx. 300 meters. Within each one of them there is a 250 kW isolated step-up DC-DC converter and six Maximum Power Point Tracking (MPPT) boost converters. The converter control and global DC station control are specially developed for this project. To validate the controls, a HIL test bench is developed at SuperGrid Institute with: - A detailed model of one complete DC station (MPPT and isolated DC-DC), running on FPGA (sample time: 110 ns) thanks to eHs gen5. - Averaged models of solar panels and network components: DC-AC converter, 2 other DC stations and cables, running on CPU (sample time: 50 us) thanks to Hypersim. At RT23, the HIL test bench and Software In the Loop results (start-up, nominal operating state, shutdown) will be presented and some perspectives of the project, including the ambition to build a digital twin to the MVDC network will be given.

RT23 | HIL validation of advanced voltage controller of DC/DC converters in an MTDC grid

Author : Asimenia Korompili

The presentation demonstrates the HiL validation of the active disturbance rejection control (ADRC) applied for the voltage regulation of DC/DC converters in a three-terminal DC grid. The ADRC is a disturbance oberver-based control, which estimates the total disturbance and rejects it through the feedback controller. The main HiL set-up consists of two OPAL-RT targets, the OP5707 and the OP4510. In the FPGA of OP5707 target the DC grid is modelled, with one buck converter, one boost converter and one constant power load (CPL). The OP5707 target provides analog measurements to the OP4510 target. In the CPU of the OP4510 target, the ADRC voltage digital controllers of the buck and the boost converters are modelled, as well as the PID current digital controller of the CPL. In the FPGA of this OPAL-RT target the PWM signals of the DC/DC converters are generated. The OP4510 target provides the digital switching signals to the DC/DC converters modelled in the OP5707 target. The PWM signals of the two ADRC-controlled converters, generated both in OP4510 target, are shifted randomly for a more realistic representation of non-synchronised PWM of different converters in the grid. The HiL results are compared with the results of offline simulations of the continuous system and of the discrete system, with/without digital controllers. The effect of delays, noise and PWM modelling in these simulations is also investigated. The same HiL set-up and the comparison approach is followed for two different ADRC models, one linear and one non-linear. These challenge differently the control discretisation and thus the realisation of the digital controllers in the OPAL-RT target. The HiL results validate both ADRC models, as compared to the offline simulations. It is proven that the digital controllers manage to estimate fast the total disturbance and reject it through the feedback control, to handle different disturbances in the DC grid in real time, while providing very good dynamics and tight voltage regulation.


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